Edocti Training

AUTOSAR Application Modeling and RTE Generation

Name: AUTOSAR Application Modeling and RTE Generation
Rating: 4.5 (124 reviews)

Intermediate

14 h

4.5 (124 reviews)

Scheduled sessions

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AUTOSAR RTE in practice: Learn to architect complex Software Components (SWCs) and generate the Runtime Environment (RTE) end-to-end.

Connect abstract Virtual Function Bus (VFB) concepts—ports, interfaces, and runnables—with concrete ARXML configuration and code implementation.

Integrate applications with the Basic Software (BSW) stack for communication, I/O, and diagnostics while mastering strict timing constraints.

Gain practical experience: ~70% of the training is dedicated to focused labs covering modeling, mapping, and automated generation phases.

How this helps: Design clear, standardized interfaces and orchestrate cross-component execution and communication with total confidence.

Who it’s for: Embedded and automotive engineers transitioning into application-layer design or RTE integration roles.

The curriculum includes high-value tips for performance optimization, footprint reduction, and troubleshooting common ARXML structural issues.

Skills You Will Learn

SWC Modeling & Composition Virtual Function Bus (VFB) RTE API Implementation OS Task Mapping BSW Stack Integration ARXML Authoring Communication Paradigms RTE Generation Flow

Curriculum

AUTOSAR fundamentals

Core concepts and architecture overview
Application layer vs. BSW; role of RTE and VFB
Terminology: SWC, ports, port interfaces, runnables, events

BSW concepts – essentials for application engineers

BSW layers at a glance (EcuM, BswM, SchM, OS overview)
Communication stack overview: Com, PduR, CanIf/EthIf, CanTp/SoAd
Diagnostics & error handling: Dcm, Dem (high-level)
Memory stack basics: MemIf, NvM, Fee/Ea, MemMap

Application layer modeling

SWC types: Sender–Receiver, Client–Server, Mode management, NvData
VFB modeling: components, compositions, connections
Ports & port interfaces (data elements, operations, mode declarations)
Variants and feature models (variant handling)
Runnables & events: timing, data received, operation invoked, mode switch
Task mapping: scheduling runnables on OS tasks; priorities and timing

RTE – interface and execution model

How the RTE mediates Application ↔ BSW; call-outs and call-ins
APIs overview: Rte_Read/Rte_Write, Rte_Call, Rte_Switch, Rte_IrvRead/Write
Wait points and RTE events; reentrancy and concurrency considerations
Operating modes for RTE; performance and footprint tips

I/O and communication integration

I/O basics: DIO/ADC/PWM – when an SWC accesses I/O via RTE
Communication paradigms and signal/PDU modeling in Com
CAN and Ethernet data exchange; BSW configuration touchpoints
End-to-end data paths (SWC ↔ RTE ↔ ComStack) – tracing and test hooks

RTE generation flow

Authoring: ARXML structure and validation basics
Configuration: mapping ports, connectors, events, tasks
Generation phases and artifacts; integrating generated code into the build
Hands-on: generate RTE and run a minimal SWC composition
Troubleshooting: typical errors (inconsistent ARXML, missing mappings)

Course Day Structure

Part 1: 09:00–10:30
Break: 10:30–10:45
Part 2: 10:45–12:15
Lunch break: 12:15–13:15
Part 3: 13:15–15:15
Break: 15:15–15:30
Part 4: 15:30–17:30