Edocti Training
Practical RTOS and RT programming
Scheduled sessions
Starts:
Nov 3, 2026
, 4 days
€ 550
Enroll
Skills You Will Learn
RTOS Architecture
Task Scheduling
Multithreading & Sync
POSIX IPC
QNX Momentics
Multicore Optimization
Real-Time Latency
Hardware Deployment
Curriculum
Practical RTOS intro
- Time-triggered embedded systems
- RTOS introduction
- Schedulers: main techniques; priority inheritance; stack sharing
- Simple scheduler implementations to understand data structures and context switching
- Basic rules of real-time applications (dos and don'ts)
The first QNX project
- Implement a producer–consumer with timeout guarantees in Momentics
- Run, deploy to target, debug, profile
- Basic QNX commands and partitioning
- Goal: get used to the QNX development environment
The Neutrino architecture
- High‑level overview of key Neutrino components (table of contents for deeper modules)
The INTEGRITY RTOS architecture
- A short module that highlights unique INTEGRITY features
Threads and processes
- Processes vs. threads; creation
- Thread synchronization: joins, mutexes, semaphores, condition variables, read–write locks, sleepon locks, barriers
- Controlling wait times (timeouts, absolute vs. relative)
- QNX thread pools
Time, timers and clocks
- Core data structures for timekeeping
- Kernel time: periodic operation, clock ticks
- Timers for time‑triggered applications
- Kernel timeouts and waiting states
IPC programming
- POSIX IPC: data transfer and shared memory
- Synchronization: semaphores, events, signals, file locks, named mutexes
- Neutrino‑specific IPC
Multicore topics
- Designing applications for multicore
- Scheduling and interrupts on multicore
- Processor affinity
- Inter‑core synchronization
Creating a QNX image
- Build and customize a QNX image for BeagleBone
Application: sensor network with real‑time constraints
- Team build: star topology, data processing
- Over‑the‑network real‑time constraints
Optional modules
Advanced real‑time topics (optional)
- Scheduling theory: Rate‑Monotonic, Deadline‑Monotonic, EDF; response‑time analysis
- Resource access protocols: Priority Inheritance vs. Priority Ceiling; bounded blocking
- Latency and jitter measurement: cyclictest; high‑res timers; clock selection
- Tracing and profiling: LTTng, perf, ftrace; flame graphs; system‑wide timing diagrams
- Lock‑free queues and ring buffers for ISR ↔ main; memory barriers; cache effects
- Interrupt affinity, CPU isolation, and predictable multicore behavior
- DMA and zero‑copy paths; determinism of I/O
- Time synchronization for distributed RT systems: PTP/IEEE‑1588
- Safety and coding standards: MISRA C, defensive programming, static analysis
- QNX specifics: adaptive partitioning, SchedFIFO/SchedRR/Sporadic Server, pulses, channels
Course Day Structure
- Part 1: 09:00–10:30
- Break: 10:30–10:45
- Part 2: 10:45–12:15
- Lunch break: 12:15–13:15
- Part 3: 13:15–15:15
- Break: 15:15–15:30
- Part 4: 15:30–17:30